Alif Semiconductor /AE512F80F5582AS_CM55_HP_View /ETH /ETH_MAC_Q0_TX_FLOW_CTRL

Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. Full-Duplex Mode: In the full-duplex mode, this bit should be read as 0x0 before writing to this register. To initiate a Pause packet, the application must set this bit to 0x1. During Control packet transfer, this bit continues to be set to indicate that a packet transmission is in progress. When Pause packet transmission is complete, the MAC resets this bit to 0x0. The user should not write to this register until this bit is cleared. Half-Duplex Mode: When this bit is set (and TFE bit is set) in the half-duplex mode, the MAC asserts the backpressure. During backpressure, when the MAC receives a new packet, the transmitter starts sending a JAM pattern resulting in a collision. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

0 (Val_0x0): Flow control busy or backpressure activate is disabled

1 (Val_0x1): Flow control busy or backpressure activate is enabled

Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to Tx Pause packets. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause packets. Half-Duplex Mode: In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled.

0 (Val_0x0): Transmit flow control is disabled

1 (Val_0x1): Transmit flow control is enabled

Pause Low Threshold This field configures the automatic retransmission interval of the Pause packet. The value should always be less than the Pause Time configured in the PT field. For example, if PT = 0x100 (256 slot times), and PLT = 0x1, a second Pause packet is automatically transmitted at 228 (256-28) slot times after the first Pause packet is transmitted. The following list provides the threshold values for different values.The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the RMII interface. This (approximate) computation is based on the packet size (64, 1518, 2000, 9018, 16384, or 32768) + 2 Pause Packet Size + IPG in Slot Times.

0 (Val_0x0): Pause time minus 4 slot times (PT - 4 slot times)

1 (Val_0x1): Pause time minus 28 slot times (PT - 28 slot times)

2 (Val_0x2): Pause time minus 36 slot times (PT - 36 slot times)

3 (Val_0x3): Pause time minus 144 slot times (PT - 144 slot times)

4 (Val_0x4): Pause time minus 256 slot times (PT - 256 slot times)

5 (Val_0x5): Pause time minus 512 slot times (PT - 512 slot times)

Disable Zero-Quanta Pause When this bit is set, it disables the automatic generation of the zero-quanta Pause packets. When this bit is reset, normal operation with automatic zero-quanta Pause packet generation is enabled.

0 (Val_0x0): Zero-quanta pause packet generation is enabled

1 (Val_0x1): Zero-quanta pause packet generation is disabled

Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the RMII clock domain, consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.